4 Megabit (512K x 8-Bit) SRAM
F
IGURE
4. T
IMING
W
AVEFORM OF
R
EAD
C
YCLE(2)
(WE = V
IH
)
32C408B
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
Memory
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ(max)
is less than t
LZ(min)
both for a given device and from device to device.
5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = V
IL
.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention is necessary during read and
write cycle.
F
IGURE
5. SRAM H
EAVY
I
ON
C
ROSS
S
ECTION
05.02.02 Rev 7
All data sheets are subject to change without notice
7
©2002 Maxwell Technologies
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
