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MX29LV040CQI-90G 参数 Datasheet PDF下载

MX29LV040CQI-90G图片预览
型号: MX29LV040CQI-90G
PDF下载: 下载PDF文件 查看货源
内容描述: 4M- BIT [ 512K ×8 ] CMOS单电压3V只相当于行业FLASH MEMORY [4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 52 页 / 485 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29LV040C  
this case, the system must start at the beginning of the  
algorithm when it returns to determine the status of the  
operation.  
Q2:Toggle Bit II  
The "Toggle Bit II" on Q2, when used with Q6, indicates  
whether a particular sector is actively erasing (that is,  
the Automatic Erase algorithm is in process), or whether  
that sector is erase-suspended. Toggle Bit II is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.  
Q5  
ExceededTiming Limits  
Q5 will indicate if the program or erase time has ex-  
ceeded the specified limits (internal pulse count). Under  
these conditions Q5 will produce a "1". This time-out  
condition indicates that the program or erase cycle was  
not successfully completed. Data# Polling and Toggle  
Bit are the only operating functions of the device under  
this condition.  
Q2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
system may use either OE# or CE# to control the read  
cycles.) But Q2 cannot distinguish whether the sector  
is actively erasing or is erase-suspended. Q6, by com-  
parison, indicates whether the device is actively eras-  
ing, or is in Erase Suspend, but cannot distinguish which  
sectors are selected for erasure. Thus, both status bits  
are required for sectors and mode information. Refer to  
Table 6 to compare outputs for Q2 and Q6.  
If this time-out condition occurs during sector erase op-  
eration, it specifies that a particular sector is bad and it  
may not be reused. However, other sectors are still func-  
tional and may be used for the program or erase opera-  
tion. The device must be reset to use other sectors.  
Write the Reset command sequence to the device, and  
then execute program or erase command sequence. This  
allows the system to continue to use the other active  
sectors in the device.  
Reading Toggle Bits Q6/ Q2  
Whenever the system initially begins reading toggle bit  
status, it must read Q7-Q0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has  
completed the program or erase operation. The system  
can read array data on Q7-Q0 on the following read cycle.  
If this time-out condition occurs during the chip erase  
operation, it specifies that the entire chip is bad or com-  
bination of sectors are bad.  
If this time-out condition occurs during the byte program-  
ming operation, it specifies that the entire sector con-  
taining that byte is bad and this sector maynot be re-  
used, (other sectors are still functional and can be re-  
used).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of Q5 is high  
(see the section on Q5). If it is, the system should then  
determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as Q5 went  
high. If the toggle bit is no longer toggling, the device  
has successfully completed the program or erase op-  
eration. If it is still toggling, the device did not complete  
the operation successfully, and the system must write  
the reset command to return to reading array data.  
The time-out condition will not appear if a user tries to  
program a non blank location without erasing. Please  
note that this is not a device failure condition since the  
device was incorrectly used.  
Q3  
Sector Erase Timer  
The remaining scenario is that system initially determines  
that the toggle bit is toggling and Q5 has not gone high.  
The system may continue to monitor the toggle bit and  
Q5 through successive read cycles, determining the sta-  
tus as described in the previous paragraph. Alterna-  
tively, it may choose to perform other system tasks. In  
After the completion of the initial sector erase command  
sequence, the sector erase time-out will begin. Q3 will  
remain low until the time-out is complete. Data# Polling  
andToggle Bit are valid after the initial sector erase com-  
mand sequence.  
P/N:PM1149  
REV. 1.3, APR. 24, 2006  
14