1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are a “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
t
remain LOW until PD (MIN) has been satisfied. The maximum time allowed for power-
t
t
down duration is PD (MAX) (9 × REFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
t
required NOP or DES command). CKE must be maintained HIGH until CKE has been
satisfied. A valid, executable command may be applied after power-down exit latency,
t
t
XP XPDLL have been satisfied. A summary of the power-down modes is listed in
Table 74.
For certain CKE-intensive operations, for example, repeating a power-down exit to
refresh to power-down entry sequence, the number of clock cycles between power-down
exit and power-down entry may not be sufficient enough to keep the DLL properly
t
updated. In addition to meeting PD when the REFRESH command is used in between
t
power-down exit and power-down entry, two other conditions must be met. First, XP
t
must be satisfied before issuing the REFRESH command. Second, XPDLL must be satis-
fied before the next power-down may be entered. An example is shown in Figure 108 on
page 157.
Ta b le 74:
Po w e r-Do w n Mo d e s
Po w e r-Do w n
Exit
DRAM St a t e
MR1[12] DLL St a t e
Re le va n t Pa ra m e t e rs
tXP to any other valid command
Active (any bank open)
“Don’t
Care”
On
Fast
Precharged
(all banks precharged)
1
0
On
Fast
tXP to any other valid command
Off
Slow
tXPDLL to commands that require the DLL to be locked
(READ, RDAP, or ODT on)
tXP to any other valid command
Fig u re 98: Act ive Po w e r-Do w n En t ry a n d Exit
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
t
t
t
CK
CH
CL
Command
Valid
NOP
NOP
NOP
NOP
NOP
Valid
t
PD
t
IS
t
IH
CKE
t
t
t
CKE (MIN)
IH
IS
Address
Valid
Valid
t
t
CPDED
XP
Enter power-down
mode
Exit power-down
mode
Indicates A Break in
Time Scale
Don’t Care
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
152
MDTIC [ Micon Design Technology Corporation ]
