1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
Ta b le 78:
M9
Mo d e Re g ist e rs fo r RTT_NOM
MR1 (RTT_NOM)
RTT_NOM
(RZQ)
RTT_NOM
(Oh m s)
RTT_NOM
Mo d e Re st rict io n
M6
M2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Off
Off
60
n/a
RZQ/4
Self refresh
RZQ/2
120
40
RZQ/6
RZQ/12
RZQ/8
20
Self refresh, write
30
Reserved
Reserved
Reserved
Reserved
n/a
n/a
Notes: 1. RZQ = 240Ω. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
Ta b le 79:
Mo d e Re g ist e rs fo r RTT_WR
MR2 (RTT_WR)
RTT_WR
(RZQ)
RTT_WR
(Oh m s)
M10
M9
0
0
0
1
Dynamic ODT off: WRITE does not affect RTT_NOM
RZQ/4
RZQ/2
Reserved
n/a
60
120
1
0
1
1
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Ta b le 80:
Tim in g Dia g ra m s fo r Dyn a m ic ODT
Fig u re a n d Pa g e
Tit le
Figure 111 on page 164
Figure 112 on page 164
Figure 113 on page 165
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: Without WRITE Command
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles,
BL8
Figure 114 on page 166
Figure 115 on page 166
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
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163
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