1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
The following definitions are used within the IDD measurement tables:
• LOW: VIN ≤ VIL(AC) MAX; HIGH: VIN ≥ VIH(AC) MIN
• Stable: Inputs are stable at a HIGH or LOW level
• Floating: Inputs are VREF = VDDQ/ 2
• Switching: See Tables 10 and 11
Ta b le 9:
IDD Me a su re m e n t Co n d it io n s Re fe re n ce
Ta b le Nu m b e r
Me a su re m e n t Co n d it io n s
Table 13 on page 31
Table 14 on page 33
Table 15 on page 35
Table 16 on page 37
Table 17 on page 38
IDD0 and IDD1
IDD2Ps, IDD2Pf, IDD2Q, IDD2N, IDD3P, and IDD3N
IDD4R, IDD4W
IDD5B, IDD6, IDD6ET
IDD7 (see Table 18 on page 38)
Ta b le 10:
De fin it io n o f Sw it ch in g fo r Co m m a n d a n d Ad d re ss In p u t Sig n a ls
Sw it ch in g fo r Ad d re ss (Ro w /Co lu m n ) a n d Co m m a n d Sig n a ls (CS#, RAS#, CAS#, a n d /o r WE#)
Address (row/column)
If not otherwise stated, inputs are stable at HIGH or LOW during 4 clocks and then change to
the opposite value (Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax . . . )
Bank address
If not otherwise stated, the bank addresses should be switched in a similar fashion as the
row/column addresses
Command
(CS#, RAS#, CAS#, WE#)
Define command background pattern = D D D D D D D D D D D D . . . where:
D = (CS#, RAS#, CAS#, WE#) = (HIGH, LOW, LOW, LOW)
D = (CS#, RAS#, CAS#, WE#) = (HIGH, HIGH, HIGH, HIGH)
If other commands are necessary (ACTIVATE for IDD0 or READ for IDD4R), the background
pattern command is substituted by the respective CS#, RAS#, CAS#, and WE# levels of the
necessary command
Ta b le 11:
De fin it io n o f Sw it ch in g fo r Da t a Pin s
Sw it ch in g fo r Da t a Pin s (DQ, DQS, DM)
Data strobe (DQS)
Data (DQ)
Data strobe is changing between HIGH and LOW after every clock cycle
Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for
DQ signals, which means that data DQ is stable during one clock
Data masking (DM)
No switching; DM must always be driven LOW
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
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