Micrel, Inc.
9-BIT SHIFT
REGISTER
SY10E142
SY100E142
SY10E142
SY100E142
FEATURES
s
700MHz min. shift frequency
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
9 bits wide for byte-parity applications
s
Asynchronous Master Reset
s
Dual clocks
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
Ω
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E142
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E142 are high-speed 9-bit shift registers
designed for use in new, high-performance ECL systems.
The E142 can accept serial or parallel data to be shifted out
in one direction as both serial and parallel outputs. The
nine inputs, D
0
-D
8
, accept parallel input data, while S-IN
accepts serial input data.
The SEL (Select) control pin serves to determine the
mode of operation, either SHIFT or LOAD. The shift direction
is from bit 0 to bit 8. The input data has to meet the set-up
time before being clocked into the nine input registers on
the rising edge of CLK
1
or CLK
2
. Shifting is also performed
on the rising edge of either CLK
1
or CLK
2
. The MR (Master
Reset) control signal asynchronously resets all nine
registers to a logic LOW when a logic HIGH is applied to
MR.
The E142 is designed for applications such as diagnostic
scan registers, parallel-to-serial conversions and is also
suitable for byte-wide parity.
BLOCK DIAGRAM
S-IN
D
0
1
0
D Q
Q
0
1
D
1
0
D Q
Q
1
PIN NAMES
Pin
Function
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
V
CC
to Output
1
D
2
0
D Q
Q
2
D
0
-D
8
S-IN
1
D
3
0
D Q
Q
3
SEL
CLK
1
, CLK
2
MR
1
D
4
0
D Q
Q
4
Q
0
-Q
8
V
CCO
1
D
5
0
D Q
Q
5
1
D
6
0
D Q
Q
6
1
D
7
0
D Q
Q
7
1
D
8
SEL
CLK1
CLK2
MR
0
D Q
Q
8
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: March 2006