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SY100EP33VKCTR 参数 Datasheet PDF下载

SY100EP33VKCTR图片预览
型号: SY100EP33VKCTR
PDF下载: 下载PDF文件 查看货源
内容描述: 5V / 3.3V的4GHz , ± 4 PECL / LVPECL除法 [5V/3.3V 4GHz, ± 4 PECL/LVPECL DIVIDER]
分类和应用: 预分频器多谐振动器逻辑集成电路光电二极管时钟
文件页数/大小: 9 页 / 88 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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Micrel, Inc.
5V/3.3V 4GHz,
÷
4 PECL/LVPECL DIVIDER
Precision Edge
®
SY10EP33V
Precision Edge
®
SY100EP33V
SY10EP33V
SY100EP33V
FEATURES
s
Guaranteed maximum frequency >4GHz
s
3.3V and 5V power supply options
s
Guaranteed propagation delay <460ps over
temperature
s
Wide operating temperature range: –40
°
C to +85
°
C
s
Available in 8-pin MSOP and SOIC packages
ECL Pro™
DESCRIPTION
The SY10/100EP33V is an integrated
÷4
divider.
The V
BB
pin, an internally generated voltage supply,
is available to this device only. For single-ended input
conditions, the unused differential input is connected to
V
BB
as a switching reference voltage. V
BB
may also rebias
AC-coupled inputs. When used, decouple V
BB
to V
CC
via
a 0.01µF capacitor and limit current sourcing or sinking
to 0.5mA. When not used, V
BB
should be left open.
The reset pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the reset allows for the
synchronous use of multiple EP33s in a system.
The 100K Series includes internal temperature
compensation circuitry.
PIN NAMES
Pin
CLK, /CLK
RESET
V
BB
Q, /Q
Function
ECL Clock Inputs with Internal 75kΩ
Pull-Down Resistor, Default State is LOW
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
TRUTH TABLE
(1)
CLK
X
/CLK
X
RESET
Z
(2)
L
Notes:
1. F = Divide by 4 function.
2. Z = Low to High transition.
Q
L
F
/Q
H
F
ECL Pro are trademarks of Micrel, Inc.
Precision Edge is a registered trademarks of Micrel, Inc.
M9999-071906
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: July 2006