ML4824
PIN CONFIGURATION
ML4824
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
IEAO
IAC
ISENSE
VRMS
SS
VDC
RAMP 1
RAMP 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEAO
VFB
VREF
VCC
PFC OUT
PWM OUT
GND
DC ILIMIT
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
2
3
4
5
6
7
8
IEAO
I
AC
I
SENSE
V
RMS
SS
V
DC
RAMP 1
RAMP 2
PFC transconductance current error
amplifier output
PFC gain control reference input
9
10
11
DC I
LIMIT
GND
PWM current limit comparator input
Ground
PWM OUT PWM driver output
PFC OUT
V
CC
V
REF
V
FB
VEAO
PFC driver output
Positive supply (connected to an
internal shunt regulator)
Buffered output for the internal 7.5V
reference
PFC transconductance voltage error
amplifier input
PFC transconductance voltage error
amplifier output
Current sense input to the PFC current
limit comparator
Input for PFC RMS line voltage
compensation
Connection point for the PWM soft start
capacitor
PWM voltage feedback input
Oscillator timing node; timing set
by R
T
C
T
When in current mode, this pin
functions as as the current sense input;
when in voltage mode, it is the PWM
input from PFC output (feed forward
ramp).
12
13
14
15
16
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
