ML4826
PIN CONFIGURATION
ML4826
20-Pin PDIP (P20)
20-Pin SOIC (S20)
IEAO
I
AC
I
SENSE
V
RMS
SS
V
DC
R
T
C
T
RAMP 1
RAMP 2
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VEAO
V
FB
V
REF
V
CC2
V
CC1
PFC OUT
PWM 1
PWM 2
PGND
AGND
DC I
LIMIT
10
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
2
3
4
5
6
7
8
9
IEAO
I
AC
I
SENSE
V
RMS
SS
V
DC
R
T
C
T
RAMP 1
RAMP 2
PFC transconductance current error
amplifier output
PFC gain control reference input
Current sense input to the PFC current
limit comparator
Input for PFC RMS line voltage
compensation
Connection point for the PWM soft start
capacitor
PWM voltage feedback input
Connection for oscillator frequency
setting components
PFC ramp input
11
12
13
14
15
16
17
18
19
AGND
PGND
PWM 2
PWM 1
PFC OUT
V
CC2
V
CC1
V
REF
V
FB
VEAO
Analog signal ground
Return for the PWM totem-pole
outputs
PWM driver 2 output
PWM drive 1 output
PFC driver output
Positive supply for the PWM drive
outputs
Positive supply (connected to an
internal shunt regulator).
Buffered output for the internal 7.5V
reference
PFC transconductance voltage error
amplifier input
PFC transconductance voltage error
amplifier output
When in current mode, this pin
functions as the current sense input;
when in voltage mode, it is the PWM
input from the PFC output (feedforward
ramp)
PWM current limit comparator input
20
10
DC I
LIMIT
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
