March 1997
ML6691*
100BASE-T MII-to-PMD Transceiver
GENERAL DESCRIPTION
The ML6691 implements the upper portion of the physical
layer for the Fast Ethernet 100BASE-T standard. Functions
contained in the ML6691 include a 4B/5B encoder/
decoder, a Stream Cipher scrambler/descrambler, and
collision detect. Additional functions of the ML6691 —
accessible through the two-wire MII management
interface — include full duplex operation, loopback,
power down mode, and MII isolation.
The ML6691 is designed to interface to a 100BASE-T
Ethernet Media Access Controller (MAC) via the MII
(Media Independent Interface) on one side, and a
100BASE-X PMD transceiver on the other side. A
complete 100BASE-TX physical layer (PHY) solution is
realized using the ML6691, the ML6673, and one of the
available clock recovery/generation devices. A 100BASE-
FX physical layer solution is implemented by disabling the
scrambler function of the ML6691 and using an external
optical PMD.
FEATURES
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Conforms to the Fast Ethernet 100BASE-T
IEEE 802.3µ standard
Integrated 4B/5B encoder/decoder
Integrated Stream Cipher scrambler/descrambler
Compliant MII interface
Two-wire serial interface management port for
configuration and control
On-chip 25 MHz crystal oscillator
Interfaces to either AMD’s PDT/PDR (AM79865/79866)
or Motorola’s FCG (MC68836)
Used with ML6673 for 100BASE-TX solutions
44-pin PLCC package
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
TXC
OSC
V
CC
GND
TXCLK
TXD3
...
TXD0
NIBBLE
INPUT
REGISTER
4B/5B
ENCODER
STREAM
CIPHER
SCRAMBLER
SYMBOL
OUTPUT
REGISTER
TSM4
...
TSM0
SD
TXEN
TXER
COL
CRS
RXDV
RXER
TRANSMIT
STATE
MACHINE
COLLISION
DETECTION
RECEIVE
STATE
MACHINE
DCFR
RXCLK
RXD3
...
RXD0
NIBBLE
OUTPUT
REGISTER
5B/4B
DECODER
SYMBOL
ALIGNER
STREAM
CIPHER
DESCRAMBLER
SYMBOL
INPUT
REGISTER
RSM4
...
RSM0
RXC
ISOLATE
FULLDUP
COLTST
LPBK
LINK FAILED
MDIO
MDC
MANAGEMENT SECTION
CONTROL
STATUS
CS
LPBK
LOCAL
AD4...AD0
RST
1