24C01A/02A/04A
FIGURE 6-1:
BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
S
A
C
K
A
C
K
A
C
K
P
BUS ACTIVITY
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 1
DATA n + 7
S
T
O
P
SDA LINE
BUS ACTIVITY
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
7.0
ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for flow diagram.
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
DS11183D-page 6
©
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
