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24LC515-I/SM 参数 Datasheet PDF下载

24LC515-I/SM图片预览
型号: 24LC515-I/SM
PDF下载: 下载PDF文件 查看货源
内容描述: 512K I2C™ CMOS串行EEPROM [512K I2C™ CMOS Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 24 页 / 333 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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24AA515/24LC515/24FC515
2.0
PIN DESCRIPTIONS
2.4
Serial Clock (SCL)
The descriptions of the pins are listed in Table 2-1.
This input is used to synchronize the data transfer from
and to the device.
TABLE 2-1:
A0
A1
A2
1
2
3
PIN FUNCTION TABLE
Function
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard wired to
logical
1
state (V
CC
). Device
will not operate with this pin
left floating or held to logical
0
(V
SS
).
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+2.5 to 5.5V (24FC515)
Name PDIP SOIJ
1
2
3
2.5
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
V
SS
SDA
SCL
WP
V
CC
4
5
6
7
8
4
5
6
7
8
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2.1
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
©
2008 Microchip Technology Inc.
DS21673G-page 5