24AA65/24LC65/24C65
FIGURE 8-1:
Control Byte
1 0 1 0 A A A R/W
2 1 0
CONTROL SEQUENCE BIT ASSIGNMENTS
Address Byte 1
S 0 0 A A A A A
12 11 10 9 8
Address Byte 0
A
A
7 • • • • • • 0
Configuration Byte
R X X B B B B
3 2 1 0
Slave Device
Address Select
Bits
S/HE
Block
Count
Security Read
S
t
a
r
t
Acknowledges from Device
R
Acknowledge
from
Master
Data from Device
No
ACK
S
t
Data from Device
o
p
A
A
A
A
A
1 0 1 0 A A A 0
C
1 X X X X X X X
C
X X X X X X X X
C
1 1 X X X X X X
C
1 1 1 1 B B B B
C
1 1 1 1 N N N N
2 1 0
3 2 1 0
3 2 1 0
K
K
K
K
K
S/HE
Starting Block
Number
Number of
Blocks to
Protect
Security Write
S
t
a
r
t
Acknowledges from Device
R
A
A
A
A
1 0 1 0 A A A 0
C
1 X X B B B B X
C
X X X X X X X X
C
1 0 X X N N N N
C
3 2 1 0
K
2 1 0
3 2 1 0
K
K
K
S
t
o
p
S/HE
Starting Block
Number
Number of
Blocks to
Protect
High Endurance Block Read
S
t
a
r
t
Acknowledges from Device
R
No
ACK
Data from Device
S
t
o
p
A
A
A
A
1 0 1 0 A A A 0
C
1 X X X X X X X
C
X X X X X X X X
C
0 1 X X X X X X
C
1 1 1 1 B B B B
2 1 0
3 2 1 0
K
K
K
K
S/HE
High Endurance
Block Number
High Endurance Block Write
S
t
a
r
t
Acknowledges from Device
R
A
A
A
A
1 0 1 0 A A A 0
C
1 X X B B B B X
C
X X X X X X X X
C
0 0 X X 0 0 0 0
C
1 0
2
3 2 1 0
K
K
K
K
S
t
o
p
High Endurance
Block Number
S/HE
DS21073J-page 12
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
