MCP23016
1.7.2
OUTPUT LATCH REGISTERS
Two registers provide access to the two port output
latches:
• OLAT0 (provides access to the output latch for
port GP0)
• OLAT1 (provides access to the output latch for
port GP1)
A read from these registers results in a read of the latch
that controls the output and not the actual port. A write
to these registers updates the output latch that controls
the output.
REGISTER 1-3:
R/W-0
OL0.7
bit 7
bit 7-0
OLAT0 - OUTPUT LATCH REGISTER 0
R/W-0
OL0.6
R/W-0
OL0.5
R/W-0
OL0.4
R/W-0
OL0.3
R/W-0
OL0.2
R/W-0
OL0.1
R/W-0
OL0.0
bit 0
OL0.0:O0.7:
Reflects the logic level on the output latch.
1
= Logic ‘1’
0
= Logic ‘0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 1-4:
R/W-0
OL1.7
bit 7
bit 7-0
OLAT1 - OUTPUT LATCH REGISTER 1
R/W-0
OL1.6
R/W-0
OL1.5
R/W-0
OL1.4
R/W-0
OL1.3
R/W-0
OL1.2
R/W-0
OL1.1
R/W-0
OL1.0
bit 0
OL1.0:O1.7:
Reflects the logic level on the output latch.
1
= Logic ‘1’
0
= Logic ‘0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
©
2007 Microchip Technology Inc.
DS20090C-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
