PIC12C5XX
TABLE 1-1:
PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674
Maximum
Frequency
of Operation
(MHz)
EPROM
Program
Memory
RAM Data
Memory
(bytes)
EEPROM
Data Memory
(bytes)
Peripherals
Timer
Module(s)
A/D Con-
verter (8-bit)
Channels
Wake-up
from SLEEP
on pin
change
Interrupt
Sources
Features
I/O Pins
Input Pins
Internal
Pull-ups
In-Circuit
Serial
Programming
Number of
Instructions
Packages
4
4
4
4
4
10
10
10
10
Clock
512 x 12
1024 x 12
1024 x 12
(ROM)
41
512 x 12
1024 x 12
1024 x 14
2048 x 14
1024 x 14
2048 x 14
Memory
25
41
25
41
128
128
128
128
—
—
—
16
16
—
—
16
16
TMR0
—
TMR0
—
TMR0
—
TMR0
—
TMR0
—
TMR0
4
TMR0
4
TMR0
4
TMR0
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
5
1
Yes
Yes
—
5
1
Yes
Yes
—
5
1
Yes
—
5
1
Yes
Yes
5
1
Yes
Yes
4
5
1
Yes
Yes
4
5
1
Yes
Yes
4
5
1
Yes
Yes
4
5
1
Yes
Yes
33
8-pin DIP,
JW, SOIC
33
8-pin DIP,
JW, SOIC
33
8-pin DIP,
SOIC
33
8-pin DIP,
JW, SOIC
33
8-pin DIP,
JW, SOIC
35
8-pin DIP,
JW, SOIC
35
8-pin DIP,
JW, SOIC
35
8-pin DIP,
JW
35
8-pin DIP,
JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
©
1999 Microchip Technology Inc.
DS40139E-page 5