PIC18F2480/2580/4480/4580
15.1
Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(=
0),
Timer3 increments on every internal instruction
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 15-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
1
T1OSO/T13CKI
F
OSC
/4
Internal
Clock
T1OSCEN
(1)
T3CKPS<1:0>
T3SYNC
TMR3ON
TMR3CS
1
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
T1OSI
0
Sleep Input
Timer3
On/Off
CCP/ECCP Special Event Trigger
T3ECCP1
Clear TMR3
TMR3L
TMR3
High Byte
Set
TMR3IF
on Overflow
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 15-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 clock input
1
1
F
OSC
/4
Internal
Clock
T1OSCEN
(1)
T3CKPS<1:0>
T3SYNC
TMR3ON
CCP/ECCP Special Event Trigger
T3ECCP1
Clear TMR3
TMR3L
TMR3
High Byte
8
Set
TMR3IF
on Overflow
TMR3CS
T1OSO/T13CKI
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
T1OSI
0
Sleep Input
Timer3
On/Off
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39637D-page 164
©
2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
