PIC18F2480/2580/4480/4580
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
8.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
The basic process is shown in Example 8-1.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.
8.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 8-2 must be followed to initiate the write cycle.
8.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
EXAMPLE 8-1:
DATA EEPROM READ
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADR
EECON1, EEPGD ; Point to DATA memory
;
; Data Memory Address to read
BCF
BSF
MOVF
EECON1, CFGS
EECON1, RD
EEDATA, W
; Access EEPROM
; EEPROM Read
; W = EEDATA
EXAMPLE 8-2:
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADR
;
; Data Memory Address to write
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
BCF
BSF
; Enable writes
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
; Disable Interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
BTFSC
BRA
BSF
INTCON, GIE
; Enable Interrupts
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
© 2009 Microchip Technology Inc.
DS39637D-page 113
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