PIC18F2480/2580/4480/4580
16.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
The CCP1 module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP1,
but is equally applicable to ECCP1.
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode, described in
apply to ECCP1 only.
PIC18F2480/2580 devices have one CCP module.
PIC18F4480/4580
devices
have
two
CCP
(Capture/Compare/PWM) modules. CCP1, discussed
in this chapter, implements standard Capture,
Compare and Pulse-Width Modulation (PWM) modes.
ECCP1 implements an Enhanced PWM mode. The
ECCP implementation is discussed in
REGISTER 16-1:
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
—
R/W-0
DC1B1
R/W-0
DC1B0
R/W-0
CCP1M3
R/W-0
CCP1M2
R/W-0
CCP1M1
R/W-0
CCP1M0
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented:
Read as ‘0’
DC1B<1:0>:
CCP1 Module PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC1B<9:2>) of the duty cycle are found in CCPR1L.
CCP1M<3:0>:
CCP1 Module Mode Select bits
0000
= Capture/Compare/PWM disabled (resets CCP1 module)
0001
= Reserved
0010
= Compare mode; toggle output on match (CCP1IF bit is set)
0011
= Reserved
0100
= Capture mode; every falling edge or CAN message received (time-stamp)
(1)
0101
= Capture mode; every rising edge or CAN message received (time-stamp)
(1)
0110
= Capture mode; every 4th rising edge or every 4th CAN message received (time-stamp)
(1)
0111
= Capture mode; every 16th rising edge or every 16th CAN message received (time-stamp)
(1)
1000
= Compare mode; initialize CCP1 pin low; on compare match, force CCP1 pin high
(CCPIF bit is set)
1001
= Compare mode; initialize CCP pin high; on compare match, force CCP1 pin low
(CCPIF bit is set)
1010
= Compare mode; generate software interrupt on compare match (CCP1IF bit is set,
CCP1 pin reflects I/O state)
1011
= Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set)
11xx
= PWM mode
Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source.
bit 3-0
Note 1:
©
2009 Microchip Technology Inc.
DS39637D-page 167
MICROCHIP [ MICROCHIP TECHNOLOGY ]
