TC500/A/510/514
FIGURE 4-1:
T
TIME
Converter Status
Integrator 0
Voltage V
INT
Comparator Delay
Auto-Zero
Integrate
Full Scale Input
Reference
De-integrate
Overshoot Integrator
Output
Zero
TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING
Comparator
Output
Undefined
0 For Negative Input
1 For Postive Input
A
AB Inputs
B
Controller
Operation
A=0
B=1
A=1
A=1
B=1
A=0
B=0
B=0
Begin Conversion with
Auto-Zero Phase
Time Input
Integration
Phase
Sample Input Polarity
T
INT
Capture
De-integration
Time
Integrator
Output
Zero Phase
Complete
Ready for Next
Conversion
(Auto-Zero is
Idle State)
Typically = T
INT
(Positive Input Shown)
Comparator Delay +
Processor Latency
Minimizing
Overshoot
will Minimize
I.O.Z. Time
Notes:
The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
2002 Microchip Technology Inc.
DS21428B-page 9
©
MICROCHIP [ MICROCHIP TECHNOLOGY ]
