P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
SG1842/SG1843 Series
C
U R R E N T - M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
TYPICAL APPLICATION CIRCUITS (continued)
VCC
V
IN
SG1842/43
7(12)
VO
5V
8(14)
5V
UVLO
S
5V
R
REF
R
T
INTERNAL
BIAS
2.5V
2N222A
VREF
GOOD LOGIC
7(11)
6(10)
R
SLOPE
4(7)
CT
Q1
OSCILLATOR
From VO
C.S.
2R
COMP
R
i
2(3)
1V
ERROR
AMP
R
5(8)
3(5)
PWM
LATCH
R
d
CF
R
F
R
1(1)
C
R
S
5(9)
FIGURE 23. — SLOPE COMPENSATION
Due to inherent instability of current mode converters running above 5ꢁꢀ duty cycle, a slope compensation should be added to
either current sense pin or the error amplifier. Figure 23 shows a typical slope compensation technique.
VREF
R
T
VCC
A
SG1842/ 43
2N2222
4.7K
1K
COMP
VREF
1
2
3
4
8
7
6
5
100K
VFB
VCC
0.1µF 0.1µF
ERROR AMP
ADJUST
1K
5K
OUTPUT
4.7K
I
OUTPUT
GROUND
SENSE
I
SENSE
ADJUST
R CT
T
GROUND
CT
FIGURE 24. — OPEN LOOP LABORATORY FIXTURE
High-peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
Copyright © 2000
Rev. 1.6 4/00
13
MICROSEMI [ Microsemi ]
