P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
UC184xA/284xA/384xA
C U R R E N T M O D E P W M C O N T R O L L E R
P R O D U C T I O N D A T A S H E E T
TYPICAL APPLICATION CIRCUITS (continued)
FIGURE 6. — SLOPE COMPENSATION
VCC
DC BUS
UCx84xA
7(12)
VO
5V
8(14)
RT
UVLO
S
5V
REF
R
INTERNAL
BIAS
2.5V
2N222A
VREF
GOOD LOGIC
7(11)
6(10)
RSLOPE
4(7)
OSCILLATOR
Q1
From VO
CT
C.S.
COMP
2R
Ri
2(3)
RF
1V
ERROR
AMP
R
5(8)
3(5)
PWM
LATCH
Rd
CF
R
1(1)
C
RS
5(9)
Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either
the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.
FIGURE 7. — OPEN LOOP LABORATORY FIXTURE
VREF
RT
VCC
A
UCx84xA
2N2222
100K
4.7K
1K
COMP
VREF
1
2
3
4
8
7
6
5
VFB
VCC
0.1µF
0.1µF
ERROR AMP
ADJUST
1K
5K
ISENSE
ADJUST
OUTPUT
4.7K
ISENSE
OUTPUT
GROUND
RTCT
GROUND
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Copyright © 1995
Rev. 1.2 12/95
7
MICROSEMI [ Microsemi ]
