SRAM
MT5C6405
+5V
+5V
480
AC TEST CONDITIONS
480
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
Q
Q
30pF
255
5 pF
255
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
7. At any given temperature and voltage condition,
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
tHZCE is less than tLZCE, and tHZWE is less than tLZWE
8. WE\ is HIGH for READ cycle.
.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform
is inverted.
unloaded, and f =
1
Hz.
tRC (MIN)
t
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tHZCE, tHZOE and tHZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±200mV typical from
steady state voltage, allowing for actual tester RC time con-
stant.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM
MIN
MAX UNITS NOTES
2
---
V
VCC for Retention Data
VDR
CE\ > (VCC - 0.2V)
IN > (VCC - 0.2V)
or < 0.2V
Data Retention Current
1
mA
VCC = 2V ICCDR
V
Chip Deselect to Data
Retention Time
tCDR
tR
0
---
ns
ns
4
Operation Recovery Time
4, 11
tRC
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tCDR
tR
VIH
VIL
VDR
CE\
DON’T CARE
UNDEFINED
Micross Components reserves the right to change products or specifications without notice.
MT5C6405
Rev. 2.2 01/10
5
MICROSS [ MICROSS COMPONENTS ]
