MITSUBISHI <Dig./Ana. INTERFACE>
M62392P,FP
8-BIT 12CH I
2
C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
I2C BUS LINE CHARACTERISTICS
Symbol
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
SCL clock frequency
Time the bus must be free before a new transmission can start
Hold time START Condition. After this period,the first clock
pulse is generated.
LOW period of the clock
HIGh period of the clock
Set-up time for START condition (Only relevant for a repeated
START condition)
Hold time DATA
Set-up time DATA
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Set-up time for STOP condition
Parameter
Normal mode
Min.
0
4.7
Max.
100
-
High speed mode
Min.
0
1.3
Max.
400
-
units
KHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
4.0
4.7
4.0
4.7
0
250
-
-
4.0
-
-
-
-
-
-
1000
300
-
0.6
1.3
0.6
4.7
0
100
20+
20+
0.6
-
-
-
-
0.9
-
300
300
-
*Note that a transmitter must internally provide at least a hold time to bridge the undefined
region (max.300 ns) of the falling edge of SCL.
TIMING CHART
t
R,
t
F
t
BUF
V
IH
SDA
V
IL
t
HD:STA
V
IH
SCL
t
SU:DAT
t
HD:DAT
t
SU:STA
t
SU:STO
V
IL
t
LOW
START
t
HIGH
START
STOP
START
MITSUBISHI ELECTRIC
1997-5-27C.rev ( 4 / 7 )
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
