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M64894GP 参数 Datasheet PDF下载

M64894GP图片预览
型号: M64894GP
PDF下载: 下载PDF文件 查看货源
内容描述: 串行输入锁相环频率合成器TV / VCR [SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR]
分类和应用: 录像机电视输入元件
文件页数/大小: 8 页 / 51 K
品牌: MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
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MITSUBISHI IC
S
(TV)
M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DATA CORDING EXAMPLE
Write mode format example
Byte
Address Byte
Devider Byte1
Devider Byte2
Control Byte1
Band SW Byte
MSB
1
0
1
1
0
LSB
1
1
1
1
1
Condotion in data setting
ADS input V
CC1
Dividing ratio N=16544
C.P. current 270µA
f
REF
division ratio 1/1024
BS4 output ON
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
f
VCO
=N×8×f
REF
=16544×8×(4MHz/1024)=517MHz
Read mode format example
Byte
Address Byte
Status Byte1 input
Status Byte1 output
MSB
1
1
0
LSB
1
1
1
Condotion in divise
1
1
1
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
FL “1”output at locked ADC input at open
TEST MODE DATA SET UP METHOD
Test Mode Bit Set Up
X
: Random, 0 or 1. normal "0"
RSa, RSb : Set up for the reference frequency division ratio
RSa
1
0
RSb
1
1
0
Division ratio
1/512
1/1024
1/640
MA1 ,MA0 : Programmabule Address Bit
Address input voltage
0 to 0.1∗V
CC1
Always valid
0.4∗V
CC1
to 0.6*V
CC1
0.9∗V
CC1
to V
CC1
MA1
0
0
1
1
MA0
0
1
0
1
X
OS : Set up the tuning amplifier
OS
0
1
POR
Tuning voltage output
ON
OFF
: Power on reset flag. “1” output at reset
: Lock detecter flag. “1” output at locked,
“0” output at unlocked
Mode
Normal
Test
N14 to N0 : How to set dividing ratio of the programable the divider
Dividing ratio N=N14(2
14
=16384)+
⋅⋅⋅
+N0(2
0
=1)
Therefore, the range of division N is 1,024 to 32,768
Example) fvco=f
REF
×8×N
=3.90625×8×N
=31.25×N (kHz)
CP: Setting up the charge pump current of the phase
comparator
CP
0
1
Charge pump current
70µA
270µA
Mode
Test
Normal
FL
A2, A1, A0: 5level A/D converter output data
ADC input voltage
0.6∗V
CC1
to V
CC1
0.45∗V
CC1
to 0.6∗V
CC1
0.3∗V
CC1
to 0.45∗V
CC1
0.15∗V
CC1
to 0.3∗V
CC1
0 to 0.15∗V
CC1
A2
1
0
0
0
0
A1
0
1
1
0
0
A0
0
1
0
1
0
The voltage accuracy allowance range:
±0.03∗V
CC1
(V)
T2, T1, T0 : Setting up for the test mode
T2 T1 T0
0 0 X
0 1 X
1 1 0
1 1 1
1 0 0
1 0 1
Charge pump
Normal operation
POWER ON RESET OPERATION
Mode
Normal operation
High impedance
Sink
Source
High impedance
High impedance
Pin 12 condition
ADC input
ADC input
ADC input
ADC input
f
REF
output
f1/N output
(Initial state the power is turned ON)
BS4 to BS1
Charge pump
Tuning amplifier
Charge pump current
: OFF
: High impedance
: OFF
: 270µA
Test mode
Test mode
Test mode
Test mode
Test mode
Frequency division ratio : 1/1024
6