MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
temperature protection circuit.
The over temperature function pro-
vides effective protection against
overloads and cooling system fail-
ures in most applications. However,
it does not guarantee that the maxi-
mum junction temperature rating of
the IGBT chip will never be ex-
ceeded. In cases of abnormally
high losses such as failure of the
system controller to properly regu-
late current or excessively high
switching frequency it is possible
for IGBT chip to exceed T
j(max)
be-
fore the base plate reaches the OT
trip level.
Caution:
Tripping of the over-temperature
protection is an indication of stress-
ful operation. Repetitive tripping
should be avoided.
6.4.4 Over-Current Protection
The IPM uses current sense IGBT
chips to continuously monitor
power device current. If the current
though the Intelligent Power Mod-
ule exceeds the specified
overcurrent trip level (OC) for a pe-
riod longer than t
off(OC)
the IPMs
internal control circuit will protect
the power device by disabling the
gate drive and generating a fault
output signal. The timing of the
over-current protection is shown in
Figure 6.17. The t
off(OC)
delay is
implemented in order to avoid trip-
ping of the OC protection on short
pulses of current above the OC
level that are not dangerous for the
power device. When an over-cur-
rent is detected a controlled shut-
down is initiated and a fault output
is generated. The controlled shut-
down lowers the turn-off di/dt which
helps to control transient voltages
that can occur during
shut down from high fault currents.
Most Intelligent Modules use the
two step shutdown depicted in Fig-
ure 6.17. In the two step shutdown,
the gate voltage is reduced to an
Figure 6.15
INPUT
SIGNAL
intermediate voltage causing the
current through the device to drop
slowly to a low level. Then, about
5µs later, the gate voltage is re-
duced to zero completing the shut
down. Some of the large six and
seven pack IPMs use an active
ramp of gate voltage to achieve the
desired reduction in turn off di/dt
under high fault currents. The oscil-
lographs in Figure 6.18 illustrate
Operation of Under-Voltage Lockout
UV
r
UV
t
CONTROL
SUPPLY
VOLTAGE
FAULT
OUTPUT
CURRENT
(I
FO
)
t
FO
t
dUV
t
FO
t
dUV
INTERNAL
GATE
VOLTAGE
V
GE
CONTROL SUPPLY ON
SHORT
GLITCH
IGNORED
POWER SUPPLY
FAULT AND
RECOVERY
CONTROL SUPPLY OFF
Figure 6.16
INPUT
SIGNAL
Operation of Over-Temperature
BASE PLATE
TEMPERATURE
(Tb)
OT
OT
r
FAULT OUTPUT
CURRENT
(I
FO
)
INTERNAL
GATE
VOLTAGE
V
GE
Sep.1998
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
