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MC10H131L 参数 Datasheet PDF下载

MC10H131L图片预览
型号: MC10H131L
PDF下载: 下载PDF文件 查看货源
内容描述: 双D型主从触发器 [Dual D Type Master-Slave Flip-Flop]
分类和应用: 触发器锁存器逻辑集成电路
文件页数/大小: 4 页 / 102 K
品牌: MOTOROLA [ MOTOROLA, INC ]
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D Type Master-Slave
Flip-Flop
The MC10H131 is a MECL 10H part which is a functional/pinout duplication
of the standard MECL 10K family part, with 100% improvement in clock speed
and propagation delay and no increase in power–supply current.
Propagation Delay, 1.0 ns Typical
Power Dissipation, 235 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
Symbol
VEE
VI
Iout
TA
Tstg
Rating
–8.0 to 0
0 to VEE
50
100
0 to +75
–55 to +150
–55 to +165
Unit
Vdc
Vdc
mA
°C
°C
°C
MC10H131
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
S1 5
D1 7
CE1 6
Q1
Q1
R1 4
CC 9
R2 13
Q2
CE2 11
D2 10
S2 12
Q2
2
3
ELECTRICAL CHARACTERISTICS
(VEE = –5.2 V
±5%)
(See Note)
Characteristic
Power Supply Current
Input Current High
Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
Symbol
IE
IinH
IinL
VOH
VOL
VIH
VIL
0.5
–1.02
–1.95
–1.17
–1.95
530
660
485
790
–0.84
–1.63
–0.84
–1.48
0.5
–0.98
–1.95
–1.13
–1.95
310
390
285
465
–0.81
–1.63
–0.81
–1.48
0.3
–0.92
–1.95
–1.07
–1.95
310
390
285
465
–0.735
–1.60
–0.735
–1.45
µA
Vdc
Vdc
Vdc
Vdc
Min
Max
62
Min
25°
Max
56
Min
75°
Max
62
Unit
mA
µA
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
14
15
RS TRUTH TABLE
R
L
L
H
H
S
L
H
L
H
Qn+1
Qn
H
L
N.D.
CLOCKED TRUTH TABLE
C
L
H
H
D
X
L
H
Qn+1
Qn
L
H
C = CE + CC
A clock H is a clock transition
from a low to a high state.
AC PARAMETERS
Propagation Delay
Clock, CE
Set, Reset
Rise Time
Fall Time
Set–up Time
Hold Time
Toggle Frequency
tpd
0.8
0.6
tr
tf
tset
thold
ftog
0.6
0.6
0.7
0.8
250
1.6
1.6
2.0
2.0
0.8
0.7
0.6
0.6
0.7
0.8
250
1.7
1.7
2.0
2.0
0.8
0.7
0.6
0.6
0.7
0.8
250
1.8
1.8
2.2
2.2
ns
ns
ns
ns
MHz
ns
N.D. = Not Defined
DIP
PIN ASSIGNMENT
VCC1
Q1
Q1
R1
S1
CE1
D1
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
Q2
Q2
R2
S2
CE2
D2
CC
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
©
Motorola, Inc. 1996
2–69
REV 5