MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NAND Gate
High–Performance Silicon–Gate CMOS
The MC54/74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
MC54/74HC00A
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
14
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 32 FETs or 8 Equivalent Gates
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
LOGIC DIAGRAM
14
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
4
6
5
9
8
10
12
11
13
PIN 14 = VCC
PIN 7 = GND
Y4
Y3
Y2
Y = AB
Y1
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
Pinout: 14–Lead Packages
(Top View)
VCC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
10/95
©
Motorola, Inc. 1995
1
REV 7
MOTOROLA [ MOTOROLA, INC ]
