MC54/74HC573A
SWITCHING WAVEFORMS
VCC
tr
INPUT D
tPLH
Q
tTLH
90%
50%
10%
tTHL
Q
50%
90%
50%
10%
tPHL
tPLH
tPHL
tf
VCC
GND
LATCH
ENABLE
50%
GND
tw
Figure 1.
Figure 2.
OUTPUT
ENABLE
3.0 V
50%
GND
tPZL
tPLZ
INPUT D
HIGH
IMPEDANCE
10%
90%
VOL
VOH
HIGH
IMPEDANCE
LATCH
ENABLE
50%
GND
tSU
50%
GND
th
VCC
VALID
VCC
Q
50%
tPZH
tPHZ
Q
1.3 V
Figure 3.
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
D0
2
EXPANDED LOGIC DIAGRAM
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
D
Q
LE
11
19
Q0
CL*
D1
3
18
Q1
D2
* Includes all probe and jig capacitance
4
17
Q2
D3
5
16
Q3
Figure 5. Test Circuit
D4
6
15
Q4
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kΩ
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
D5
7
14
Q5
D6
8
13
Q6
CL*
D7
9
12
Q7
* Includes all probe and jig capacitance
LATCH ENABLE
Figure 6. Test Circuit
OUTPUT ENABLE
1
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MOTOROLA [ MOTOROLA, INC ]
