MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB23P06V/D
TMOS
Power Field Effect Transistor
D2PAK for Surface Mount
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
•
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
•
Faster Switching than E–FET Predecessors
™
Data Sheet
V
™
MTB23P06V
Motorola Preferred Device
P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
23 AMPERES
60 VOLTS
RDS(on) = 0.120 OHM
TM
D
G
S
CASE 418B–02, Style 2
D2PAK
Features Common to TMOS V and TMOS E–FETS
•
Avalanche Energy Specified
•
IDSS and VDS(on) Specified at Elevated Temperature
•
Static Parameters are the Same for both TMOS V and TMOS E–FET
•
Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage
— Non–repetitive (tp
≤
10 ms)
Drain Current — Continuous @ 25°C
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25
Ω)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
60
60
±
15
±
25
23
15
81
90
0.60
3.0
– 55 to 175
794
1.67
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
°C/W
TJ, Tstg
EAS
R
θJC
R
θJA
R
θJA
TL
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
©
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MOTOROLA [ MOTOROLA, INC ]
