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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Motorola Interconnect Bus  
OR — Bit Error Flag  
0 = No bit error has been detected.  
1 = A bit error has been detected.  
This bit is set when a push field bit value on the MI Bus does not  
match the bit value that was sent. This is known as an MI Bus bit  
error. OR does not generate an interrupt request in MI Bus mode.  
NF — Noise Error Flag  
0 = No noise detected.  
1 = Noise detected.  
This bit is set when noise is detected on the receive line during an  
MI Bus pull field.  
Bit 7  
SCSWAI  
0
6
MIE  
0
5
MDL1  
0
4
MDL0  
0
3
0
0
2
0
0
1
0
0
Bit 0  
RAF  
0
RESET:  
SC0SR2 — MI Bus Status Register 2  
$00C5  
Read anytime. Write has no meaning or effect.  
SCSWAI — Serial Communications Interface Stop in WAIT Mode  
0 = SCI clock operates normally.  
1 = Halt SCI clock generation when in WAIT mode.  
MIE — Motorola Interface Bus (MI Bus) Enable  
0 = The SCI functions normally.  
1 = MI Bus is enabled for this subsystem.  
When MIE is set, the SCI0 registers, bits and pins assume the  
functionality required for MI Bus.  
MDL1, MDL0 — MI Bus delay select  
These bits are used to set up the delay for the start of the NRZ receive  
for MI Bus operation as shown (for a 20kHz bit rate) in the following  
table.  
Advance Information  
274  
68HC(9)12D60 — Rev 4.0  
Motorola Interconnect Bus  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com