Freescale Semiconductor, Inc.
General Description
VRH1
VRL1
VDDAD
VSSAD
VRH0
VRL0
VDDAD
VSSAD
VRH0
60K byte flash EEPROM *
VFP*§
ATD1
ATD0
VRL0
$
60K byte ROM
VDDAD
VSSAD
2K byte RAM
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
1K byte EEPROM
CPU12
Periodic interrupt
Single-wire
background
debug module
IOC0
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
COP watchdog
Clock monitor
Breakpoints
BKGD
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
Enhanced
capture
timer
XFC
VDDPLL
VSSPLL
PLL
RxD0
TxD0
RxD1
TxD1
PS0
PS1
PS2
PS3
SCI0 (MI BUS)
SCI1
Lite
EXTAL
XTAL
integration
module
(LIM)
RESET
SISO/MISO
MOMI/MOSI
SCK
PS4
PS5
PS6
PS7
SPI
SS
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
PW0
PW1
PW2
PW3
PP0
PP1
PP2
PP3
LSTRB/TAGLO
ECLK
PWM
MODA/IPIPE0
MODB/IPIPE1/CGMTST
DBE/CAL/ECLK
PP4
PP5
PP6
PP7
I/O
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
Multiplexed Address/Data Bus
DDRA
DDRB
TxCAN
PCAN1
PORT A
PORT B
CAN
RxCANPCAN0
PG7
KWG6
KWG5
KWG4
PG4
PH4
KWG3
VDD ×2
KWG2
VSS ×2
KWG1
KWG0
PGPUD(VDD)
Wide
bus
Power for internal circuitry
KWH7
KWH6
VDDX ×2
VSSX ×2
KWH5
KWH4
KWH3
KWH2
Power for I/O drivers
Narrow bus
KWH1
KWH0
PHPUD(VSS)
Notes:
* 68HC912D60 only
$ 68HC12D60 only
§ On the 68HC12D60 this pin is not connected and can be tied to 5V or 12V without effect.
Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. These in-
ternal pins should either be defined as outputs or have their pull-ups/downs enabled.
Figure 1-2. 68HC(9)12D60 80-pin QFP Block Diagram
Advance Information
30
68HC(9)12D60 — Rev 4.0
MOTOROLA
General Description
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MOTOROLA [ MOTOROLA ]
