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XPC850DSLCZT50BU 参数 Datasheet PDF下载

XPC850DSLCZT50BU图片预览
型号: XPC850DSLCZT50BU
PDF下载: 下载PDF文件 查看货源
内容描述: 通信控制器硬件规格 [Communications Controller Hardware Specifications]
分类和应用: 通信控制器外围集成电路时钟
文件页数/大小: 76 页 / 778 K
品牌: MOTOROLA [ MOTOROLA, INC ]
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Layout Practices
Part VI Bus Signal Timing
Table 6-6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80
MHz. Timing information for other bus speeds can be interpolated by equation using the
MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must
be operated in half-speed bus mode (for example, an MPC850 used at 66 MHz must be
configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated
by 1 ns per 10 pF. Derating calculations can also be performed using the MPC850 Electrical
Specifications Spreadsheet.
Table 6-6. Bus Operation Timing
1
50 MHz
Num
B1
B1a
Characteristic
Min
CLKOUT period
EXTCLK to CLKOUT phase
skew (EXTCLK > 15 MHz and
MF <= 2)
EXTCLK to CLKOUT phase
skew (EXTCLK > 10 MHz and
MF < 10)
CLKOUT phase jitter (EXTCLK
> 15 MHz and MF <= 2)
2
CLKOUT phase jitter
2
CLKOUT frequency jitter (MF <
10)
2
CLKOUT frequency jitter (10 <
MF < 500)
2
CLKOUT frequency jitter (MF >
500)
2
Frequency jitter on EXTCLK
3
CLKOUT pulse width low
CLKOUT width high
CLKOUT rise time
CLKOUT fall time
CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] invalid
20
-0.90
Max
0.90
Min
30.30
-0.90
Max
0.90
Min
25
-0.90
Max
0.90
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
50.00
Unit
ns
ns
B1b
-2.30
2.30
-2.30
2.30
-2.30
2.30
50.00
ns
B1c
B1d
B1e
B1f
B1g
B1h
B2
B3
B4
B5
B7
-0.60
-2.00
8.00
8.00
5.00
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
-0.60
-2.00
12.12
12.12
7.58
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
-0.60
-2.00
10.00
10.00
6.25
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
0.250
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
ns
ns
%
%
%
%
ns
ns
ns
ns
ns
B7a
CLKOUT to TSIZ[0–1], REG,
5.00
RSV, AT[0–3], BDIP, PTR invalid
7.58
6.25
0.250
50.00
ns
12
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA