LANCAM A/L series (not recommended for new designs)
Pin Descriptions
/MI (Match Input, Input, TTL)
/FI (Full Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied
LOW.
/MA (Device Match Flag, Output, TTL)
/RESET (Reset, Input, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare
cycle. The /MA output is not qualified by /EC or /MI, and
reflects the match flag from that specific device’s Status
register. /MA is reset when the active register set is
changed.
/RESET must be driven LOW to place the device in a
known state before operation, which resets the device to
the conditions shown in Table 3 on page 11. The /RESET
pin should be driven by TTL levels, not directly by an RC
timeout. /E must be kept HIGH during /RESET.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare
cycle. The /MM output is not qualified by /EC or /MI, and
reflects the multiple match flag from that specific device’s
Status register. /MM is reset when the active register set is
changed.
TEST1, TEST2 (Test, Input, TTL)
These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.
VCC, GND (Positive Power Supply, Ground)
/FF (Full Flag, Output, TTL)
These pins are the power supply connections to the
LANCAM. VCC must meet the voltage supply
requirements in the Operating Conditions section relative
to the GND pins, which are at 0 volts (system reference
potential), for correct operation of the device. All the
ground and power pins must be connected to their
respective planes with adequate bulk and high frequency
bypassing capacitors in close proximity to the device.
If enabled in the Control register, the /FF output goes
LOW when no empty memory locations exist within the
device (and in the daisy chain above the device as
indicated by the /FI pin). The System Full flag is the /FF
pin of the last device in the daisy chain, and the Next Free
address resides in the device with /FI LOW and /FF
HIGH. If disabled in the Control register, the /FF output
only depends on the /FI input (/FF = /FI).
4
Rev. 1
MUSIC [ MUSIC SEMICONDUCTORS ]
