WidePort LANCAM
®
Family
OPERATIONAL CHARACTERISTICS
Continued
Cycle Type /E
Cmd Write L
/CM /W
L
L
I/O Status SPS SPD TCO Operation
Notes
IN
Load Instruction decoder
1
IN
2
ü
Load Address register
2
IN
ü
Load Control register
2
IN
ü
Load Page Address register
2
IN
ü
Load Segment Control register
IN
2
ü
Load Device Select register
IN
Deselected
9
OUT
3
ü
Read Next Free Address register
3
OUT
ü
Read Address register
4
OUT
Read Status Register bits 31–0
3
OUT
ü
Read Control register
OUT
3
ü
Read Page Address register
OUT
3
ü
Read Segment Control register
OUT
3
ü
Read Device Select register
3, 10
OUT
ü
Read Current Persistent Source or Destination
9
HIGH-Z
Deselected
5, 8
IN
Load Comparand register
ü
IN
Load Mask Register 1
6, 8
ü
IN
Load Mask Register 2
6, 8
ü
IN
Write Memory Array at address
6, 8
ü
6, 8
IN
Write Memory Array at Next Free address
ü
6, 8
IN
Write Memory Array at Highest-Priority match
ü
9
IN
Deselected
OUT
Read Comparand register
5, 8
ü
OUT
Read Mask Register 1
7, 8
ü
OUT
Read Mask Register 2
ü
7, 8
7, 8
OUT
Read Memory Array at address
ü
7, 8
OUT
Read Memory Array at Highest-Priority match
ü
HIGH-Z
Deselected
9
HIGH-Z
Deselected
Cmd Read
L
L
H
Data Write
L
H
L
Data Read
L
H
H
H
X
X
Notes:
1. Default Command Write cycle destination (does not require a TCO instruction).
2. To load a value into a register using a TCO instruction takes one Command Write cycle with the “f” bit equal to 1, and
the value to be loaded into the selected register placed in DQ15–0.
3. Reading the contents of a register using a TCO instruction takes two cycles. The first cycle is a Command Write of a
TCO instruction with the “f” bit equal to 0. If the next cycle is a Command Read, the value stored in the selected register
will be read out on the DQ15–0 lines. Additionally, bits 31–16 of the Status register will be read out on the DQ31–16 lines,
except in the case of a Page Address read where 0s will be read on DQ31–16 instead.
4. Default Command Read cycle source (does not require a TCO instruction).
5. Default persistent source and destination after Reset. If other resources were sources or destinations, SPD CR or SPS
CR restores the Comparand register as the destination or source.
6. Selected by executing a Select Persistent Destination instruction.
7. Selected by executing a Select Persistent Source instruction.
8. Access is performed in one or two 32-bit Read or Write cycles. The Segment Control register is used to control the
selection of the desired 32-bit segement(s) by establishing the Segment counters’ limits and start values.
9. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device
Select register is set to FFFFH which allows only write access to the device, except in the case of a match. (Writes to
the Device Select register are always active.) Device may also be deselected under locked daisy chain conditions as
shown in Tables 6a and 6b.
10. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a
persistant source or destination. The TCO PS instruction will also read back the Device ID.
Table 4: Input/Output Operations
Rev. 2
8
MUSIC [ MUSIC SEMICONDUCTORS ]
