MU9C4480A/L
OPERATIONAL CHARACTERISTICS Continued
/E
/W
/CM
/EC
DQ15-0
DA TA OU T
Figure 3: Read Cycle
/E
/W
/C M
/EC
D Q15–0
Figure 4: Write Cycle
ASS OC IAT ED DATA
READ CYCL E
STATUS READ
C YC L E
COM PARAN D W RIT E
C YC L E
/E
/CM
/W
DQ15–0
DATA
DA TA
DA TA
/EC
/M F
MAT CH FLAG VALID
/MA, /MM
/MA A ND /MM FL AGS UPDAT ED
Figure 5: Cycle to Cycle Timing Example
I/O CYCLES
the cycle by the falling edge of /E. Figures 3 and 4 show
Read and Write cycles respectively. Figure 5 shows typical
cycle-to-cycle timing with the Match flag valid at the end
of the Comparand Write. Data writes and reads to the
comparand, mask registers or memory occur in one to four
16-bit cycles, depending on the settings in the Segment
Control register. The Compare operation automatically
occurs during Data writes to the Comparand or mask
registers when the destination segment counter reaches
the end count set in the Segment Control register. If there
was a match, the second cycle reads status or associated
data, depending on the state of /CM. For cascaded devices,
The LANCAM supports four basic I/O cycles: Data Read,
Data Write, Command Read, and Command Write. The type of
cycle is determined by the states of the /W and /CM control
inputs. These signals are registered at the beginning of a cycle
by the falling edge of /E. Table 2 on page 2 shows how the /W
and /CM signals select the cycle type.
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
Rev. 3a
12
MUSIC [ MUSIC SEMICONDUCTORS ]
