Pin Descriptions
MU9C8338A 10/100Mb Ethernet Filter Interface
PIN DESCRIPTIONS
Note:
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.
GND
/RESET
INCR
VDD
/ INTR
PROC_RDY
/PCS
/PCSS
/WRITE
A6
A7
GND
126
120
144
138
132
114
VDD
RP0
RP1
RP2
RP3
GND
RP4
RP5
RP6
VDD
RP7
RP8
RP9
RP10
RP11
RP12
GND
RP13
RP14
RP15
RP_DV
VDD
NC
SC_ENB
TST_HLD
GND
TST_HLD2
NC
VDD
RP_NXT
RP_SEL
GND
NC
NC
NC
GND
1
D12
D13
D14
GND
108
A0
A1
A2
VDD
A3
A4
A5
D0
D1
D2
D3
D4
D5
VDD
D6
D7
D8
D9
D10
D11
6
102
12
96
18
90
24
84
30
78
42
48
54
60
66
MII Interface
Note:
The MII interface does not know if the system PHY is operating in Full Duplex, Half Duplex or Loopback mode. Therefore, in
applications that use Half Duplex or Loopback mode, care must be taken to ensure that unnecessary MII frames are not placed on the
interface. It is recommended that only valid Receive Frames are allowed to be sent to the MU9C8338A.
RXD[3:0] (Receive Data, Input, TTL)
RX_ER (Receive Error, Input, TTL)
RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).
RX_DV (Receive Data Valid, Input, TTL)
Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
Rev. 0a
VDD
REJ
FRX_ER
TP_SD
TP_DV
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
RXD3
RXD2
RXD1
RXD0
VDD
RX_DV
RX_CLK
RX_ER
COL
CRS
GND
TDO
GND
TDI
TMS
TCK
/TRST
VDD
Figure 2: Pinout
RX_ER indicates a data symbol error in 100Mb/s mode or
any other error that the PHY can detect, even if the MAC is
not capable of detecting that error (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
RX_CLK (Receive Clock, Input, TTL)
RX_CLK is the receive clock recovered from the data by the
PHY. It is equal to 25MHz in 100Base-X mode or 2.5MHz in
10Base-X mode.
CRS (Carrier Sense, Input, TTL)
Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx or
Tx: CRS is HIGH in 10/100Base-X half-duplex mode; for
Rx it is HIGH in repeater, full-duplex, and loopback modes.
CRS is not synchronized to RX_CLK.
3
72
36
VDD
D15
NC
/RESET_LC
/W
/E
/CM
/EC
GND
/MI
/FI
VDD
DQ0
DQ1
GND
DQ2
DQ3
DQ4
DQ5
VDD
DQ6
NC
DQ7
DQ8
DQ9
DQ10
GND
DQ11
DQ12
DQ13
NC
DQ14
DQ15
GND
SYSCLK
NC
MUSIC [ MUSIC SEMICONDUCTORS ]
