Register Descriptions
MUAC Routing CoProcessor (RCP) Family
PA:AA Bus and the Match Flags
address other than the Match address. This condition
allows rapid return to the Match address value on the
PA:AA bus lines through a RDL[HPM] cycle, without the
daisy chain having to re-resolve device-level
prioritization.
The Match flags /MF and /MM reflect the results of the
most recent Comparison cycle. During a Comparison
cycle, they do not change until after /E has gone HIGH
after which they are free to change combinatorially; their
state is not latched when /E is LOW. This condition allows
some pipelining to occur and is useful in systems with
long daisy chains. A Comparison cycle can be followed by
another cycle that does not affect the PA:AA bus before
the daisy chain is resolved. For example:
PA:AA Bus and the Status Register
The Status Register bits SR15–0 reflect the PA:AA bus
under all conditions. The Status Register flags /MF, /MM,
and /FF represent the local conditions within the device,
and are not conditioned by the /MI and /FI inputs.
CMP CR
WR CR
After a Comparison cycle, Write at Next Free address, or
access to the Highest-Priority Matching device, a Status
Register Read cycle is executed in the same device as the
active PA:AA bus. In the case of a random access Read or
Write cycle, the Status register of any selected device can
be accessed by a Read Status Register cycle. The system
designer must ensure that a Status Register Read cycle
after a random Read or Write cycle is into a single device
using Chip Select /CS1, /CS2, or the Device Select
register to prevent bus contention on the DQ31–0 bus.
The WRL CR control state can be executed before the
daisy chain has resolved device prioritization after the
CMP CR control state. The /OE then is asserted at a
suitable time, depending on the length of the daisy chain.
The Match address of the highest-priority responding
device then is driven onto the PA:AA bus.
The /MF, /MM lines continue to indicate the results of the
most recent match, even when the PA:AA bus carries an
REGISTER DESCRIPTIONS
Address Register
The Comparand register, seven mask registers, Address
register, Configuration register, Status register, Next Free
Address register, Device Select register, and Instruction
register comprise the register set. Note that all
RESERVED bits can be read and written without affecting
the operation of the device.
The 32-bit Address register is used for indirect addressing
of the Address Database. When random access to the
Address Database is restricted to indirect addressing, the
width of the control bus can be reduced to 9 bits if
masking is used or 6 bits if it is not. Control states allow
increment and decrement of the Address register as well as
auto-increment and auto-decrement Read and Write
cycles. Bits AR12–0 hold the address while bits AR31–13
are reserved and should be set LOW.
However, for forward compatibility with future product
enhancements, system designers should not rely on any
particular RESERVED bit having no effect on the
operation of the device in future revisions. Therefore all
RESERVED bits should be set to logical zero.
Configuration Register
The 32-bit Configuration register sets the persistent
operating conditions of the MUAC RCP. Bits FR31–29
select which mask register is used for direct Write cycles
to the Address database when the address is conveyed on
the AC bus (/AV=LOW), a value of 000 in this field
results in unmasked direct Write cycles. Bits FR27–26
select the mode of operation: Hardware Control mode or
Software Control mode. Bit FR25 is used to identify the
lowest-priority device in a vertically cascaded system. Bits
FR3–0 hold the device Page address. All other bits are
reserved and should be set LOW. See Table 3.
The Register Set
Comparand Register
The 64-bit Comparand register holds the value to be
compared with the valid contents of the Address Database
array, although the DQ lines can be compared directly, and
then optionally written into the Comparand register.
Mask Registers
There are seven 64-bit mask registers that are used to mask
Compare and Write cycles. When a bit is set LOW in a
selected mask register, the corresponding bit enters into
comparison during a Compare cycle, or is written during a
Write cycle. When a bit is set HIGH in a selected mask
register, the corresponding bit does not enter into
comparison during
a Compare cycle, or remains
unchanged after a Write cycle.
Rev. 4a
11
MUSIC [ MUSIC SEMICONDUCTORS ]
