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The Content Addressable Memory (CAM), High Speed
I/O Interface, Cascade Control, SRAM Interface, Test
Assess Port, and the Instruction and DQ Bus Interface
comprise the Harmony block diagram.
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The SRAM address is formed by the information obtained
from the DQ bus and either the lowest match address from
a SEARCH instruction or the address supplied by
Instruction register. The interface timing and control will
select the address from the instruction register by asserting
the applicable READ or WRITE instruction. During a
READ or WRITE instruction to the SRAM, if the
identification (UID) is the global address, then the last
CAM on the SRAM bus of the depth cascaded devices
will drive the SRAM signals (LCAM = 1).
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The CAM section of the Harmony 2M consists of 16,384
136-element ternary words, and the Harmony 1M consists
of 8,192 136-element ternary words, arranged such that
each ternary element contains a data bit and a mask bit.
The combination of data and mask bits determine whether
the ternary element address is a 0, 1, or X (don’t care).
Internally, bit 0 determines if the ternary word contains
valid data; if the bit is set to 0, then the word is available as
it does not contain valid data. This bit is used to determine
the next free address in the device.
The priority encoder generates the address of the word
with the lowest address that satisfies the match criteria
using the searched data words, CAM array words, and the
specified global mask register.
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OP[8:0] transports the instruction and its associated
parameters. DQ[67:0] is used for data transfer to, and
from, the CAM array. The DQ bus transports the search
data during the SEARCH instruction as well as the
addressing and data during the READ/WRITE operations
of the CAM array, and internal registers. The DQ bus also
carries the address information for SRAM accesses.
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The high-speed input port is a double-data rate, 68-bit,
data bus incorporated with 9-bits to encode instructions,
such as READ and WRITE. The inputs are read on the
rising edge of clock, whereas the phase input is used to
distinguish between the first and second halves of the I/O
cycle. The first half of the I/O cycle transports bits 135:68
and the second half transports bits 67:0.
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The dual data rate clock, configured as cycle A and cycle
B, allows the DQ bus interface to operate at double speed
while maintaining 100 Mhz search rates even though the
I/O width is less than the data width. Hence, only 68 pins,
instead of 136 pins, are required to support 136-bit data
words. Furthermore, Harmony can perform consecutive
searches on 136-bit data words. The phase signal ensures
that these double-speed operations are correctly aligned
with Harmony.
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The SRAM interface sections drives the address and
control signals required to access the external SRAM.
Harmony can generate a synchronous output clock
(SCLK) to perform SRAM accesses. Using the SCLK
signal Harmony reduces the amount of required interface
logic by synchronously driving the SRAM address and
control signals. When cascaded, the Harmony device
which contains a match in its Results register will drive
the SRAM bus. However, in the case where a no match
exists, the last Harmony device of the cascade (LRAM =
1) will drive the SRAM bus. Also, when cascaded, this
section also inserts pipeline delays for the SRAM address
and SRAM control for Harmony. The SRAM data bus is
connected to the appropriate host ASIC, therefore SRAM
data does not pass through Harmony.
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The cascade control section drives the cascade output
(CSO) signal when the Harmony devices are depth
cascaded. Up to eight Harmony devices can be
depth-cascaded. Harmony also contains the control logic
to determine if the entry in a single device is full or if the
table consisting of multiple devices is full. In addition, the
cascade control section provides support for multiple
matches. Although the cascade control section does not
drive the validity of matches, the success of matches,
multiple matches, or the required SRAM signals (these
signals are located in the controller section of the block
diagram), it does contain the control logic to enable the
output for these signals.
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