NJG1647HD3
!
TERMINAL INFORMATION
No.
SYMBOL
DESCRIPTION
Common RF port. This PC port is connected to P1 or P2 by logical
control voltage of CTL1.
In order to block DC bias voltage of internal circuit, an external capacitor
is required.
Control port 2. This terminal is set to +1.3~5.0V of logical high level as
usual, and set to +0.0~0.4V of logical low level for the low current
consumption mode.
Supply voltage terminal (+2.5~3.6V). Please place an inductor close to
this terminal, and a bypass capacitor between VDD and GND for
avoiding RF characteristic degradation.
Control port 1. This terminal is set to +1.3~5.0V of logical high level for
ON state between PC and P1 ports, and set to +0.0~0.4V of logical low
level for ON state between PC and P2 RF ports.
This port is connected with PC port by control voltage of
+1.3~5.0V(V
CTL(H)
) to 4th pin. An external capacitor is required to block
the DC bias voltage of internal circuit.
This port is connected to PC port by control voltage of +0.0~0.4V(V
CTL(L)
)
to 4th pin. An external capacitor is required to block the DC bias voltage
of internal circuit.
Ground terminal. Please connect this terminal with ground plane as close
as possible for good RF performance.
1
PC
2
CTL2
3
VDD
4
CTL1
5
P1
6
P2
GND
GND
-4-
NJRC [ NEW JAPAN RADIO ]
