Switching Characteristics
V
CC
e a
5 0V T
A
e a
25 C (See Section 1 for waveforms and load configurations)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Min
Propagation Delay
E to A
e
B
Propagation Delay
A
n
B
n
to A
l
B
Propagation Delay
A
n
B
n
to A
k
B
Propagation Delay
A
n
B
n
to A
e
B
C
L
e
15 pF
Max
14
14
25
22
26
21
30
32
ns
ns
ns
ns
Units
Functional Description
The ’24 5-bit comparators use combinational circuitry to di-
rectly generate ‘‘A greater than B’’ and ‘‘A less than B’’
outputs As evident from the logic diagram these outputs
are generated in only three gate delays The ‘‘A equals B’’
output is generated in one additional gate delay by decoding
the ‘‘A neither less than nor greater than B’’ condition with a
NOR gate All three outputs are activated by the active LOW
Enable Input (E)
Tying the A
l
B output from one device into an A input on
another device and the A
k
B output into the corresponding
B input permits easy expansion
The A4 and B4 inputs are the most significant inputs and
A0 B0 the least significant Thus if A4 is HIGH and B4 is
LOW the A
l
B output will be HIGH regardless of all other
inputs except E
Truth Table
Inputs
E
H
L
L
L
A
n
B
n
A
k
B
L
L
L
H
Outputs
A
l
B
L
L
H
L
A
e
B
L
H
L
L
X
X
Word A
e
Word B
Word A
l
Word B
Word B
l
Word A
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Logic Symbol
TL F 9792 – 2
V
CC
e
Pin 16
GND
e
Pin 6
3
NSC [ NATIONAL SEMICONDUCTOR ]
