ADC0808/ADC0809
Symbol
I
IN(1)
I
IN(0)
I
CC
Parameter
Conditions
Min
Typ
Max
1.0
Units
μA
μA
Logical “1” Input Current (The Control
V
IN
=15V
Inputs)
Logical “0” Input Current (The Control
V
IN
=0
Inputs)
Supply Current
f
CLK
=640 kHz
V
CC
= 4.75V
I
OUT
= −360µA
I
OUT
= −10µA
I
O
=1.6 mA
I
O
=1.2 mA
V
O
=5V
V
O
=0
−3
−1.0
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
V
OUT(1)
V
OUT(0)
V
OUT(0)
I
OUT
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “0” Output Voltage EOC
TRI-STATE Output Current
2.4
4.5
0.45
0.45
3
V
V
V
V
μA
μA
Electrical Characteristics – Timing Specifications
Timing Specifications
V
CC
=V
REF(+)
=5V, V
REF(−)
=GND, t
r
=t
f
=20 ns and T
A
=25°C unless otherwise noted.
Symbol
t
WS
t
WALE
t
s
t
H
t
D
t
H1
, t
H0
t
1H
, t
0H
t
c
f
c
t
EOC
C
IN
C
OUT
Parameter
Minimum Start Pulse Width
Minimum ALE Pulse Width
Minimum Address Set-Up Time
Minimum Address Hold Time
5)
5)
5)
5)
C
L
=50 pF, R
L
=10k (Figure
C
L
=10 pF, R
L
=10k (Figure
f
c
=640 kHz, (Figure
(Note 7)
90
10
5)
At Control Inputs
At TRI-STATE Outputs
0
10
10
Conditions
MIn
Typ
100
100
25
25
1
125
125
100
640
Max
200
200
50
50
2.5
250
250
116
1280
8 + 2 μS
15
15
Units
ns
ns
ns
ns
μs
ns
ns
μs
kHz
Clock
Periods
pF
pF
Analog MUX Delay Time From ALE R
S
=0Ω (Figure
OE Control to Q Logic State
OE Control to Hi-Z
Conversion Time
Clock Frequency
EOC Delay Time
Input Capacitance
TRI-STATE Output Capacitance
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
A Zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
.
Note 4:
Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the V
CC
n supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage
of 4.900 V
DC
over temperature variations, initial tolerance and loading.
Note 5:
Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See
None of these A/Ds requires a zero or full-scale adjust.
However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See
Note 6:
Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure
6).
See paragraph 4.0.
Note 7:
The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8:
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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