Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= 5 V
DC
unless otherwise specified.Boldface
limits apply from T
MIN
to T
MAX
;
all
other limits T
A
= T
j
= 25˚C.
ADC0844BCJ
ADC0844CCJ
Parameter
Conditions
Typ
(Note 5)
DIGITAL AND DC CHARACTERISTICS
V
OUT(0)
, Logical “0”
Output Voltage (Max)
I
OUT
, TRI-STATE Output
Current (Max)
I
SOURCE
, Output Source
Current (Min)
I
SINK
, Output Sink
Current (Min)
I
CC
, Supply Current (Max)
CS = 1, V
REF
Open
1
2.5
1
2.3
2.5
mA
V
OUT
= V
CC
16
8.0
16
9.0
8.0
mA
V
CC
= 4.75V
I
OUT
= 1.6 mA
V
OUT
= 0V
V
OUT
= 5V
V
OUT
= 0V
−0.01
0.01
−14
−3
3
−6.5
−0.01
0.01
−14
−0.3
0.3
−7.5
−3
3
−6.5
µA
µA
mA
0.4
0.34
0.4
V
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
Typ
(Note 5)
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
Limit
Units
AC Electrical Characteristics
The following specifications apply for V
CC
= 5V
DC
, t
r
= t
f
= 10 ns unless otherwise specified.
Boldface limits apply from T
MIN
to T
MAX
;
all other limits T
A
= T
j
= 25˚C.
Tested
Parameter
t
C
, Maximum Conversion Time (See Graph)
t
W(WR)
, Minimum WR Pulse Width
t
ACC
, Maximum Access Time (Delay from Falling Edge of
RD to Output Data Valid)
t
1H
, t
0H
, TRI-STATE Control (Maximum Delay from Rising
Edge of RD to Hi-Z State)
t
WI
, t
RI
, Maximum Delay from Falling Edge of WR or RD to
Reset of INTR
t
DS
, Minimum Data Set-Up Time
t
DH
, Minimum Data Hold Time
C
IN
, Capacitance of Logic Inputs
C
OUT
, Capacitance of Logic Outputs
(Note 11)
(Note 11)
50
0
5
5
100
50
ns
ns
pF
pF
(Note 11)
C
L
= 100 pF
(Note 11)
C
L
= 10 pF, R
L
= 10k
(Note 11)
(Note 11)
200
400
ns
Conditions
Typ
(Note 5)
30
50
145
125
Limit
(Note 6)
40
150
225
200
Design
Limit
(Note 7)
60
µs
ns
ns
ns
Units
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to the ground pins.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V
−
or V
IN
>
V
+
) the absolute value of the current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 4:
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5:
Typicals are at 25˚C and represent most likely parametric norm.
Note 6:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7:
Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8:
Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
Note 9:
For V
IN
(−)
≥
V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input
voltages one diode drop below ground or one diode drop greater than V
CC
supply. Be careful during testing at low V
CC
levels (4.5V), as high level analog inputs (5V)
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an
absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 10:
Off channel leakage current is measured after the channel selection.
Note 11:
The temperature coefficient is 0.3%/˚C.
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