CD4035BM CD4035BC 4-Bit Parallel-In Parallel-Out Shift Register
February 1988
CD4035BM CD4035BC
4-Bit Parallel-In Parallel-Out Shift Register
General Description
The CD4035B 4-bit parallel-in parallel-out shift register is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors This shift register is a 4-stage clocked serial reg-
ister having provisions for synchronous parallel inputs to
each stage and serial inputs to the first stage via JK logic
Register stages 2 3 and 4 are coupled in a serial ‘‘D’’ flip-
flop configuration when the register is in the serial mode
(parallel serial control low)
Parallel entry via the ‘‘D’’ line of each register stage is per-
mitted only when the parallel serial control is ‘‘high’’
In the parallel or serial mode information is transferred on
positive clock transitions
When the true complement control is ‘‘high’’ the true con-
tents of the register are available at the output terminals
When the true complement control is ‘‘low’’ the outputs are
the complements of the data in the register The true com-
plement control functions asynchronously with respect to
the clock signal
JK input logic is provided on the first stage serial input to
minimize logic requirements particularly in counting and se-
quence-generation applications With JK inputs connected
together the first stage becomes a ‘‘D’’ flip-flop An asyn-
chronous common reset is also provided
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3 0V to 15V
High noise immunity
0 45 V
DD
(typ )
Low power TTL
Fan out of 2 driving 74L
compatibility
or 1 driving 74LS
4-stage clocked operation
Synchronous parallel entry on all 4 stages
JK inputs on first stage
Asynchronous true complement control on all outputs
Reset control
Static flip-flop operation master slave configuration
Buffered outputs
Low power dissipation
5
mW
(typ ) (ceramic)
High speed
to 5 MHz
Applications
Y
Y
Y
Y
Automotive
Data terminals
Instrumentation
Medical electronics
Y
Y
Y
Y
Alarm systems
Industrial controls
Remote metering
Computers
Logic Diagram
TL F 5964 – 1
P S
e
0
e
serial mode
T C
e
1
e
true outputs
TG
e
transmission gate
Input to output is
a) A bidirectional low impedance when control input 1 is low and control input 2 is high
b) An open circuit when control input 1 is high and control input 2 is low
TL F 5964– 2
C
1995 National Semiconductor Corporation
TL F 5964
RRD-B30M105 Printed in U S A
NSC [ NATIONAL SEMICONDUCTOR ]
