Geode™ CS4210
Register Descriptions
(Continued)
4.2
REGISTER SUMMARY
values and page references where the bit formats are
found.
The tables in this subsection summarize all the registers of
the CS4210. Included in the tables are the register’s reset
Table 4-2. PCI Configuration Registers Summary
Index
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
14h-17h
Width
(Bits)
16
16
16
16
8
24
8
8
8
8
32
32
Access
R
R
RW
RW
R
R
R
RW
R
R
RW
RW
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (BAR0): Sets base address for
memory mapped OHCI Configuration Registers
Base Address Register 1 (BAR1): Sets base address for
memory mapped National Semiconductor device specific
operational registers.
Reserved
Subsystem Vendor Identification Register
Subsystem Identification Register
Reserved
Capabilities Pointer Register
Reserved
Interrupt Line Register
Interrupt Pin Register
Min Grant Register
Max Latency Register
PCI HCI Control Register
Capability ID Register
Next Item Pointer Register
Power Management Capabilities Register
Power Management and Control Status Register
Power Management CSR Bridge Support
Extension Register
Power Management Data Register
Reset Value
1000h
000Fh
0000h
0200h
03h
0C0010h
00h
50h
00h
00h
00000000h
00000000h
Reference
(Page)
18h-2B
2Ch-2Dh
2Eh-2Fh
30h-33h
34h
35h-3Bh
3Ch
3Dh
3Eh
3Fh
40h-43h
44h
45h
46h-47h
48h-49h
4Ah
4Bh
1.
2.
3.
--
16
16
--
8
--
8
8
8
8
32
8
8
16
16
8
8
--
R
R
--
R
--
RW
R
R
R
RW
R
R
R
R/W
R
R
---
1
2
---
3
---
FFh
01h
00h
00h
00h
01h
00h
4
5
00h
00h
4.
5.
The reset value must be set in the serial EEPROM to the vendor identification number assigned by the PCI SIG.
The reset value must be set in serial EEPROM to a unique number chosen by the user to represent this PCI device implementation.
The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured
by the serial EEPROM. If enabled in the EEPROM, the reset value of the register is 44h. If not enabled in the EEPROM or if no EE-
PROM is present, then the reset value is 00h.
The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured
by serial EEPROM. If enabled in the EEPROM the reset value of this register is 4000h. If not or if no EEPROM is present, then the
reset value is 000h.
The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be configured
by serial EEPROM. If enabled in the EEPROM the reset value of this register is 8000h. If not or if no EEPROM is present then the reset
value is 000h.
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