1.0 Pin Descriptions
The DP83843 pins are classified into the following interface — DEVICE CONFIGURATION INTERFACE
categories. Each interface is described in the sections that — LED INTERFACE
follow.
— PHY ADDRESS INTERFACE
— MII INTERFACE
— RESET
— 10/100 Mb/s PMD INTERFACE
— POWER AND GROUND PINS
— CLOCK INTERFACE
— SPECIAL CONNECT PINS
1.1 MII Interface
Signal Name Type
MDC
I
Pin #
35
Description
MANAGEMENT DATA CLOCK:
Synchronous clock to the MDIO management data in-
put/output serial interface which may be asynchronous to transmit and receive clocks.
The maximum clock rate is 2.5 MHz. There is no minimum clock rate.
MANAGEMENT DATA I/O:
Bi-directional management instruction/data signal that may
be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pul-
lup resistor.
CARRIER SENSE:
This pin is asserted high to indicate the presence of carrier due to
receive or transmit activities in 10BASE-T or 100BASE-X Half Duplex modes.
In Repeater or Full Duplex mode, this pin is asserted high to indicate the presence of
carrier due only to receive activity.
In Symbol mode this pin indicates the signal detect status of the TP-PMD (active high).
COL
(FXEN)
I/O, Z 21
COLLISION DETECT:
Asserted high to indicate detection of collision condition (asser-
tion of CRS due to simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s
Half Duplex modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled (bit 7, register 18h), this
pin is also asserted for a duration of approximately 1
µs
at the end of transmission to
indicate heartbeat (SQE test). During Repeater mode the heartbeat function is disabled.
In Full Duplex mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0.
There is no heartbeat function during 10 Mb/s full duplex operation.
TX_CLK
O, Z
33
TRANSMIT CLOCK:
Transmit clock output from the DP83843:
25 MHz nibble transmit clock derived from Clock Generator Module's (CGM) PLL in
100BASE-TX mode.
2.5 MHz transmit clock in 10BASE-T Nibble mode.
10 MHz transmit clock in 10BASE-T Serial mode.
TXD[3]
TXD[2]
TXD[1]
TXD[0]
TX_EN
I
I
28
29
30
31
25
TRANSMIT DATA:
Transmit data MII input pins that accept nibble data during normal
nibble-wide MII operation at either 2.5 MHz (10BASE-T mode) or 25 MHz (100BASE-X
mode).
In 10 Mb/s Serial mode, the TXD[0] pin is used as the serial data input pin, and TXD[3:1]
are ignored.
TRANSMIT ENABLE:
Active high input indicates the presence of valid nibble data on
TXD[3:0] for both 100 Mb/s or 10 Mb/s nibble mode.
In 10 Mb/s Serial mode, active high indicates the presence of valid 10 Mb/s data on
TXD[0].
TX_ER
(TXD[4])
I
24
TRANSMIT ERROR:
In 100 Mb/s mode, when this signal is high and TX_EN is active
the HALT symbol is substituted for the actual data nibble.
In 10 Mb/s mode, this input is ignored.
In Symbol mode (Symbol=0), TX_ER becomes the TXD [4] pin which is the MSB for the
transmit 5-bit data symbol.
RX_CLK
O, Z
18
RECEIVE CLOCK:
Provides the recovered receive clock for different modes of opera-
tion:
25 MHz nibble clock in 100 Mb/s mode
2.5 MHz nibble clock in 10 Mb/s nibble mode
10 MHz receive clock in 10 Mb/s serial mode
MDIO
I/O, Z 34
CRS
(SYMBOL)
I/O, Z 22
5
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