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DP8573AV 参数 Datasheet PDF下载

DP8573AV图片预览
型号: DP8573AV
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟(RTC) [Real Time Clock (RTC)]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路输出元件双倍数据速率
文件页数/大小: 16 页 / 271 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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AC Electrical Characteristics
V
CC
e
5V
g
10% V
BB
e
3V V
PFAIL
l
V
IH
C
L
e
100 pF (unless otherwise specified)
Symbol
READ TIMING
t
AR
t
RW
t
CD
t
RAH
t
RD
t
DZ
t
RCH
t
DS
WRITE TIMING
t
AW
t
WAH
t
CW
t
WW
t
DW
t
WDH
t
WCH
INTERRUPT TIMING
t
ROLL
Clock rollover to INTR out typically 16 5
ms
Address Valid before Write Strobe
Address Hold after Write Strobe (Note 9)
Chip Select to End of Write Strobe
Write Strobe Width (Note 10)
Data Valid to End of Write Strobe
Data Hold after Write Strobe (Note 9)
Chip Select Hold after Write Strobe
20
3
90
80
50
3
0
ns
ns
ns
ns
ns
ns
ns
Address Valid Prior to Read Strobe
Read Strobe Width (Note 8)
Chip Select to Data Valid Time
Address Hold after Read (Note 9)
Read Strobe to Valid Data
Read or Chip Select to TRI-STATE
Chip Select Hold after Read Strobe
Minimum Inactive Time between Read or Write Accesses
0
50
3
70
60
20
80
80
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
Units
Note 8
Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low Hence read commences when
both signals are low and terminates when either signal returns high
Note 9
Hold time is guaranteed by design but not production tested This limit is not used to calculate outgoing quality levels
Note 10
Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low Hence write commences when
both signals are low and terminates when either signal returns high
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
GND to 3 0V
6 ns (10%–90%)
1 3V
Active High
a
0 5V
Active Low
b
0 5V
Note 11
C
L
e
100 pF includes jig and scope capacitance
Note 12
S1
e
V
CC
for active low to high impedance measurements
S1
e
GND for active high to high impedance measurements
S1
e
open for all other timing measurements
Capacitance
(T
A
e
25 C
Symbol
C
IN
C
OUT
Parameter
(Note 14)
Input Capacitance
f
e
1 MHz)
TL F 9981 – 2
Typ
5
7
Units
pF
pF
Output Capacitance
Note 13
This parameter is not 100% tested
Note 14
Output rise and fall times 25 ns max (10%–90%) with 100 pF load
3