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DS90C032BTM 参数 Datasheet PDF下载

DS90C032BTM图片预览
型号: DS90C032BTM
PDF下载: 下载PDF文件 查看货源
内容描述: LVDS四通道CMOS差分线路接收器 [LVDS Quad CMOS Differential Line Receiver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 9 页 / 194 K
品牌: NSC [ NATIONAL SEMICONDUCTOR ]
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DS90C032BLVDS Quad CMOS Differential Line Receiver
September 2003
DS90C032B
LVDS Quad CMOS Differential Line Receiver
General Description
TheDS90C032B is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE
®
function
that may be used to multiplex outputs. The receiver also
supports OPEN Failsafe and terminated (100Ω) input Fail-
safe with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
The DS90C032Bprovides power-off high impedance LVDS
inputs. This feature assures minimal loading effect on the
LVDS bus lines when V
CC
is not present.
The DS90C032Band companion line driver (DS90C031B)
provide a new alternative to high power pseudo-ECL devices
for high speed point-to-point interface applications.
Features
Accepts small swing (350 mV) differential signal levels
High Impedance LVDS inputs with power down
Ultra low power dissipation
600 ps maximum differential skew (5V, 25˚C)
6.0 ns maximum propagation delay
Industrial operating temperature range
Available in surface mount packaging (SOIC)
Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n
Supports OPEN and terminated input failsafe
n
Conforms to ANSI/TIA/EIA-644 LVDS standard
n
n
n
n
n
n
n
n
n
>
155.5 Mbps (77.7 MHz) switching rates
Connection Diagram
Dual-In-Line
Functional Diagram
10099001
Order Number
DS90C032BTM
See NS Package
Number M16A
10099002
Receiver Truth Table
ENABLES
EN
L
All other
combinations
of ENABLE
inputs
EN*
H
INPUTS
R
IN+
− R
IN−
X
V
ID
0.1V
V
ID
−0.1V
Failsafe OPEN
or Terminated
OUTPUT
R
OUT
Z
H
L
H
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS100990
www.national.com