DS90CR218A/DS90CR217
Applications Information
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DS90CR218A Pin Description — Channel Link Receiver
Pin Name
PWR DWN
V
CC
GND
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
I/O
I
I
I
I
1
I
I
No.
1
4
5
1
2
1
3
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Description
TTL level input. When asserted (low input) the receiver outputs are low.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
lengths (
<
2m), the media electrical performance is less criti-
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.785 Gbit/s. Additional
applications information can be found in the following Na-
tional Interface Application Notes:
AN = ####
AN-1041
AN-1108
AN-1109
AN-806
AN-905
AN-916
Topic
Introduction to Channel Link
Channel_link PCB and Interconnect
Design-In Guidelines
Multi-Drop Channel-Link Operation
Transmission Line Theory
Transmission Line Calculations and
Differential Impedance
Cable Information
CABLES:
A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The 21-
bit CHANNEL LINK chipset (DS90CR217/218A) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR287/288A) requires five pairs of signal
wires. The ideal cable/connector interface would have a con-
stant 100Ω differential impedance throughout the path. It is
also recommended that cable skew remain below 90ps ( 85
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
plications include flat ribbon, flex, twisted pair and Twin-
Coax. All are available in a variety of configurations and op-
tions. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while Twin-
Coax is good for short and long applications. When using rib-
bon cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
www.national.com
12
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
RECEIVER FAILSAFE FEATURE:These
receivers have in-
put failsafe bias circuitry to guarantee a stable receiver out-
put for floating or terminated receiver inputs. Under these
conditions receiver inputs will be in a HIGH state. If a clock
signal is present, data outputs will all be HIGH; if the clock in-
put is also floating/terminated, data outputs will remain in the
last valid state. A floating/terminated clock input will result in
a HIGH clock output.
BOARD LAYOUT:
To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
UNUSED INPUTS:
All unused inputs at the TxIN inputs of
the transmitter may be tied to ground or left no connect. All
unused outputs at the RxOUT outputs of the receiver must
then be left floating.
NSC [ NATIONAL SEMICONDUCTOR ]
