DS90CR218A/DS90CR217
Electrical Characteristics
Symbol
I
CCTZ
Parameter
Transmitter Supply Current
Power Down
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Conditions
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
C
L
= 8 pF,
Worst Case
Pattern
(Figures
1, 3)
f = 33 MHz
f = 40 MHz
f = 66 MHz
f = 85 MHz
Min
Typ
Max
Units
TRANSMITTER SUPPLY CURRENT
10
55
µA
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current Worst
Case
49
53
78
90
140
60
65
100
115
400
mA
mA
mA
mA
µA
I
CCRZ
Receiver Supply Current Power
Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25˚C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and
∆V
OD
).
Note 4:
V
OS
previously referred as V
CM
.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
TJIT
Parameter
LVDS Low-to-High Transition Time (Figure
2)
LVDS High-to-Low Transition Time (Figure
2)
TxCLK IN Transition Time (Figure
4)
Transmitter Output Pulse Position for Bit0 (Figure
15)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure
6)
TxCLK IN High Time (Figure
6)
TxCLK IN Low Time (Figure
6)
TxIN Setup to TxCLK IN (Figure
6)
TxIN Hold to TxCLK IN (Figure
6)
TxCLK IN to TxCLK OUT Delay
@
25˚C,V
CC
=3.3V (Figure
8)
Transmitter Phase Lock Loop Set (Figure
10)
Transmitter Powerdown Delay (Figure
13)
TxCLK IN Cycle-to-Cycle Jitter
f = 85 MHz
f = 85 MHz
1.0
−0.20
1.48
3.16
4.84
6.52
8.20
9.88
11.76
0.35T
0.35T
2.5
0
3.8
6.3
10
100
2
0
1.68
3.36
5.04
6.72
8.40
10.08
T
0.5T
0.5T
Min
Typ
0.75
0.75
Max
1.5
1.5
6.0
0.20
1.88
3.56
5.24
6.92
8.60
10.28
50
0.65T
0.65T
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
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