Applications Information
MONOSTABLE OPERATION
NOTE: In monostable operation, the trigger should be driven
high before the end of timing cycle.
In this mode of operation, the timer functions as a one-shot
(Figure 1). The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a nega-
tive trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is
set which both releases the short circuit across the capacitor
and drives the output high.
DS007851-7
FIGURE 3. Time Delay
ASTABLE OPERATION
If the circuit is connected as shown in Figure 4 (pins 2 and 6
connected) it will trigger itself and free run as a multivibrator.
The external capacitor charges through RA + RB and dis-
charges through RB. Thus the duty cycle may be precisely
set by the ratio of these two resistors.
DS007851-5
FIGURE 1. Monostable
The voltage across the capacitor then increases exponen-
tially for a period of t = 1.1 RA C, at the end of which time the
voltage equals 2/3 VCC. The comparator then resets the
flip-flop which in turn discharges the capacitor and drives the
output to its low state. Figure 2 shows the waveforms gener-
ated in this mode of operation. Since the charge and the
threshold level of the comparator are both directly propor-
tional to supply voltage, the timing internal is independent of
supply.
DS007851-8
FIGURE 4. Astable
DS007851-6
In this mode of operation, the capacitor charges and dis-
charges between 1/3 VCC and 2/3 VCC. As in the triggered
mode, the charge and discharge times, and therefore the fre-
quency are independent of the supply voltage.
V
= 5V
Top Trace: Input 5V/Div.
CC
TIME = 0.1 ms/DIV.
= 9.1kΩ
Middle Trace: Output 5V/Div.
Bottom Trace: Capacitor Voltage 2V/Div.
R
A
C = 0.01µF
FIGURE 2. Monostable Waveforms
During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit so long
as the trigger input is returned high at least 10µs before the
end of the timing interval. However the circuit can be reset
during this time by the application of a negative pulse to the
reset terminal (pin 4). The output will then remain in the low
state until a trigger pulse is again applied.
When the reset function is not in use, it is recommended that
it be connected to VCC to avoid any possibility of false trig-
gering.
Figure 3 is a nomograph for easy determination of R, C val-
ues for various time delays.
7
www.national.com
NSC [ National Semiconductor ]
